View ISL59115_711120.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL59115
Data Sheet September 21, 2006 FN6185.2
Triple Channel Video Driver with LPF
The ISL59115 is a triple channel reconstruction filter with a -3dB roll-off frequency of 9MHz. Operating from a single supply ranging from +2.5V to +3.6V and drawing only 4.5mA quiescent current, the ISL59115 is ideally suited for low power, battery-operated applications. Additionally, enable pins shut the part down in under 14ns. The ISL59115 is designed to meet the bandwidth and very low power requirements of battery-operated communication, instrumentation, and modern industrial applications such as video on demand, cable set-top boxes, MP3 players, and HDTV. The ISL59115 is offered in a space-saving TQFN Pb-free package guaranteed to a 0.6mm maximum height constraint and specified for operation from -40C to +85C temperature range.
Features
* 3rd order 9MHz reconstruction filter * 40V/s slew rate * Low supply current = 4.5mA * Maximum Power-down current <0.5A * Supplies from 2.5V to 3.6V * Rail-to-rail output * TQFN package * Pb-free plus anneal available (RoHS compliant)
Applications
* Video amplifiers * Portable and handheld products * Communications devices
Pinout
ISL59115 (10 LD TQFN) TOP VIEW
GND 10
* Video on demand * Cable set-top boxes * Satellite set-top boxes * MP3 players * HDTV
YIN
1
9
YOUT
* Personal video recorder
CVBSIN
2
8
CVBSOUT
Block Diagram
+ 65mV
CIN
3
7
COUT
YIN
ENCY 4 6 ENCVBS
500mV 1uA
9MHz
-+
x2
YOUT
5 VDD
CIN + -
9MHz
65mV -+
x2
COUT
65mV
CVBSIN ENCY ENCVBS Biasing & Control
1uA
9MHz
-+
x2
CVBSOUT
Ordering Information
PART NUMBER (Note) ISL59115IRUZ-T7 FK PART MARKING TAPE AND REEL 7" TEMP. RANGE (C) -40 to +85 PACKAGE (Pb-Free) 10 Ld TQFN PKG. DWG. # L10.2.1x1.6A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59115
Absolute Maximum Ratings (TA = +25C)
Supply Voltage from VDD to GND . . . . . . . . . . . . . . . . . . . . . . . 4.2V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . VDD +0.3V to GND -0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VDD IDD_CY IDD_CVBS IDD IDD_OFF VY_CLAMP IY_DOWN IY_UP RY VCVBS_CLAMP ICVBS_DOWN ICVBS_UP RCVBS VC_CLAMP RC IC VY_SYNC VOLS AV
VDD = 3.3V, TA = +25C, RL = 150 to GND, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Supply Voltage Range Quiescent Supply Current - CY Amps Enabled Quiescent Supply Current - CVBS Amp Enabled Quiescent Supply Current Shutdown Supply Current Y Input Clamp Voltage Y Input Clamp Discharge Current Y Input Clamp Charge Current Y Input Resistance CVBS Input Clamp Voltage CVBS Input Clamp Discharge current CVBS Input Clamp Charge current CVBS Input Resistance C Input Clamp Voltage C Input Resistance C Input Bias Current Y Input Sync Detect Voltage Output Level Shift Voltage Voltage Gain C-Y Channel Gain Mismatch C/Y-CVBS Channel Gain Mismatch DC Power Supply Rejection Output Voltage High Swing Output Short-Circuit Current ENCY, ENCVBS Input Current Disable Threshold Enable Threshold Shutdown Output Impedance EN = 0V, DC EN = 0V, f = 4.5MHz VDD = 2.5V to 3.6V VIN = 2V, RL = 150 to GND VIN = 2V, to GND through 10 0V < VEN < 3.3V VIN = 0V, no load RL = 150 VIN = 500mV, ENCY = VDD, no load VIN = 500mV, ENCVBS = VDD, no load VIN = 500mV, ENCY = ENCVBS = VDD, no load ENCY = ENCVBS = 0V IY = -100A VY = 0.5V VY = -0.1V 0.5V < VY < 1V ICVBS = -100A VCVBS = 0.5V VCVBS = -0.1V 0.5V < VCVBS < 1V VY = 0.05V, IC = 0A VY = 0.05V, 0.25V < VC < 0.75V VY = 0.3V
2.5 3.1 1.4 4.5 0.1 -30 0.6 -15 1.1 -3.6 10 -30 0.6 -15 1.1 -3.6 10 500 2.0 -200 100 60 1.95 -1.75 -2 40 2.85 100 -0.2 550 2.5 -2 150 130 1.99 0.5 0.5 60 3.2 145 0.001
3.6 4.0 2.0 6.0 0.5 10 1.6 -3.0
V mA mA mA A mV A mA M
10 1.6 -3.0
mV A mA M
700 3.0 200 200 200 2.04 1.75 2
mV k nA mV mV V/V % % dB V mA
AV_CY AV_CVBS
PSRR VOH ISC IENABLE VIL VIH ROUT
+0.2 0.8
A V V
2.0 5.0 3.4 7.5
k k
2
FN6185.2 September 21, 2006
ISL59115
Electrical Specifications
PARAMETER AC PERFORMANCE BW0.1dB 0.1dB Bandwidth RSOURCE = 75, RL = 150, CL = 5pF RSOURCE = 500, RL = 150, CL = 5pF BW3dB -3dB Bandwidth RSOURCE = 75, RL = 150, CL = 5pF RSOURCE = 500, RL = 150, CL = 5pF Normalized Stopband Gain f = 27MHz, RSOURCE = 75 f = 27MHz, RSOURCE = 500 dG dP D/DT SNR TON TOFF +SR -SR tF tR Differential Gain Differential Phase Group Delay Variation Signal to Noise Ratio Enable Time Disable Time Positive Slew Rate Negative Slew Rate Fall Time Rise Time NTSC and PAL NTSC and PAL f = 100kHz, 5MHz 100% white signal VIN = 500mV, VOUT to 1% VIN = 500mV, VOUT to 1% 20% to 80%, VIN = 1V step 80% to 20%, VIN = 1V step 2.5VSTEP, 80% - 20% 2.5VSTEP, 20% - 80% 30 -30 5.6 3.9 8.8 7.8 -28.5 -30.6 0.10 0.5 5.4 65 200 14 40 -40 25 22 50 -50 MHz MHz MHz MHz dB dB % ns dB ns ns V/s V/s ns ns VDD = 3.3V, TA = +25C, RL = 150 to GND, unless otherwise specified. (Continued) CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Connection Diagram
3.3V 0.1uF VDD + Y (luminance) YIN 0.1uF
1uA 500mV
S-video cable
9MHz
65mV -+
x2
YOUT 75
YOUT 75
C (chrominance)
CIN 0.1uF + -
65mV
9MHz
-+
x2
COUT 75
COUT 75
CVBS (composite) uC or tie to 3.3V
CVBSIN 0.1uF ENCY ENCVBS Biasing & Control
1uA
9MHz
65mV -+
x2
CVBSOUT 75
CVBSOUT 75
3
FN6185.2 September 21, 2006
ISL59115 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 PIN NAME YIN CVBSIN CIN ENCY VDD ENCVBS COUT CVBSOUT YOUT GND Luminance input Composite video input Chrominance input Enable chrominance and luminance outputs Positive power supply Enable composite video output Chrominance output Composite video output Luminance output Ground DESCRIPTION
Typical Performance Curves
5 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 -0.1dB BW @ 5.6MHz -5 -10 -15 -20 -25 -30 -35 VDD = +3.3V RL = 150 100k 1M 10M FREQUENCY RESPONSE (Hz) 25M 5 0 -3dB BW @ 8.8MHz -5 -10 -15 -20 -25 -30 -35 VDD = +3.3V RL = 150 100k 1M 10M FREQUENCY RESPONSE (Hz) 35M -28dB BW @ 27MHz
FIGURE 1. GAIN vs FREQUENCY -0.1dB
FIGURE 2. GAIN vs FREQUENCY -3dB POINT
2 NORMALIZED GAIN (dB) 1 0
VDD = +3.3V RL = 150
CL = 470pF
4.0 3.5 3.0 VOUT (VP-P) 2.5 2.0 1.5 1.0 VDD = +3.3V RL = 150 FIN = 100kHz
-1 -2 -3 -4 -5 -6 100k CL = 10pF 1M 10M FREQUENCY RESPONSE (Hz) 25M CL = 100pF
0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 VIN (VP-P) 3.0 3.5 4.0
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS CLOAD
FIGURE 4. MAXIMUM OUTPUT MAGNITUDE vs INPUT MAGNITUDE
4
FN6185.2 September 21, 2006
ISL59115 Typical Performance Curves (Continued)
270 180 90 0 -90 -180 -70 -270 100k 1M 10M FREQUENCY (Hz) 100M -80 100k 1M 10M FREQUENCY (Hz) 100M GAIN (dB) -30 -40 -50 -60 VDD = +3.3V RL = 150 0 -10 -20 PHASE () VDD = +3.3V
FIGURE 5. PHASE vs FREQUENCY
FIGURE 6. PSRR vs FREQUENCY
-30 -40 -50 GAIN (dB) -60 -70 -80 -90 -100 100k
VDD = +3.3V YIN TO COUT
CIN TO YOUT 1M 10M FREQUENCY (Hz) 50M
FIGURE 7. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 8. ISOLATION vs FREQUENCY
7 SUPPLY CURRENT (mA) 6 5 4 3 2 1 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 SUPPLY VOLTAGE (V) 3.5 4.0 NO LOAD NO INPUT
FIGURE 9. MAXIMUM OUTPUT vs LOAD RESISTANCE
FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE
5
FN6185.2 September 21, 2006
ISL59115 Typical Performance Curves (Continued)
3.5 3.0 AMPLITUDE (V) VDD = +3.3V RL = 150 VOUT = 2.5VP-P TRISE = 26.4ns TFALL = 26.9ns 0 60 120 180 240 300 360 420 480 540 TIME (ns) AMPLITUDE (V) 2.5 2.0 1.5 1.0 0.5 0.0 -120 -60 1.8 1.5 1.2 0.9 0.6 0.3 0.0 -60 POSITIVE SLEW RATE = 41.1V/s NEGATIVE SLEW RATE = -40.8V/s 0 60 120 180 240 TIME (ns) 300 360 420 480 VDD = +3.3V RL = 150 VIN = 1VP-P
FIGURE 11. LARGE SIGNAL STEP RESPONSE
FIGURE 12. SLEW RATE
3.0 2.5 AMPLITUDE (V) 2.0 1.5 1.0 0.5 0.0
3.0 VDD = +3.3V RL = 150 ENABLE SIGNAL AMPLITUDE (V) 2.5 2.0 1.5 1.0 0.5 0.0 OUTPUT SIGNAL
VDD = +3.3V RL = 150 DISABLE SIGNAL
OUTPUT SIGNAL -10 0 10 TIME (ns) 20 30 40
-0.5 -60
-30
0
30
60 90 120 TIME (ns)
150
180
210
-0.5 -20
FIGURE 13. ENABLE TIME
FIGURE 14. DISABLE TIME
-20 HARMONIC DISTORTION (dBc) -30 -40 -50 -60 -70 -80 HARMONIC DISTORTION (dBc) VDD = +3.3V RL = 150 VOUT = 2VP-P THD
-30 -40 THD -50 -60 -70 2nd HD -80 0.5 1.0 1.5 2.0 2.5 OUTPUT VOLTAGE (VP-P) 3.0 3rd HD
3rd HD 2nd HD 1M FREQUENCY (Hz) 10M
FIGURE 15. HARMONIC DISTORTION vs FREQUENCY
FIGURE 16. HARMONIC DISTORTION vs OUTPUT VOLTAGE
6
FN6185.2 September 21, 2006
ISL59115 Typical Performance Curves (Continued)
16 -3dB BANDWIDTH (MHz) VDD = +3.3V RL = 150 14 12 10 8 6 4 2 80 140 200 260 320 380 440 500 VDD = +3.3V RL = 150
INPUT RESISTANCE ()
FIGURE 17. GROUP DELAY vs FREQUENCY
FIGURE 18. -3dB BANDWIDTH vs INPUT RESISTANCE
44 43 SLEW RATE (V/s) 42 41 40 39 NEGATIVE SLEW RATE 38 37 2.0 2.5 3.0 3.5 SUPPLY VOLTAGE (V) 4.0 Vout = 2VP-P RL = 150 POSITIVE SLEW RATE
FIGURE 19. SLEW RATE vs SUPPLY VOLTAGE
100 NOISE FLOOR ( nV/ Hz ) 10
2 10kHz
4
6
8
1 100kHz
2 FREQUENCY (Hz)
4
6
8
1 1MHz
2
4 4.2MHz
FIGURE 20. UNWEIGHTED NOISE FLOOR
7
FN6185.2 September 21, 2006
ISL59115 Typical Performance Curves (Continued)
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD POWER DISSIPATION (W) JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5
0.8 POWER DISSIPATION (W) 0.7
3 2.5 2 1.5 1 0.5 0
0.6 515mW 0.5 0.4 0.3 0.2 0.1 0 0 25
T QF JA N =1 94 10 C /W
775mW
J T Q
A =12
FN1 0 9C /W
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Application Information
The ISL59115 is a single-supply rail-to-rail triple (one s-video channel and one composite channel) video amplifier with internal sync tip clamps, a typical -3dB bandwidth of 9MHz and slew rate of about 40V/s. This part is ideally suited for applications requiring high composite and s-video performance with very low power consumption. As the performance characteristics and features illustrate, the ISL59115 is optimized for portable video applications.
The Sallen Key Low Pass Filter
The Sallen Key is a classic low pass configuration. This provides a very stable low pass function, and in the case of the ISL59115, a three-pole roll-off at 9MHz. The three-pole function is accomplished with an RC low pass network placed in series with and before the Sallen Key. One pole provided by the RC network and poles two and three provided by the Sallen Key for a nice three-pole roll-off at 9MHz.
Output Coupling
The ISL59115 can be AC or DC coupled to its output. When AC coupling, a 220F coupling capacitor is recommended to ensure that low frequencies are passed, preventing video "tilt" or "droop" across a line. The ISL59115's internal sync clamp makes it possible to DC couple the output to a video load, eliminating the need for any AC coupling capacitors, saving board space, cost, and eliminating any "tilt" or offset shift in the output signal. The trade off is larger supply current draw, since the DC component of the signal is now dissipated in the load resistor. Typical load current for AC coupled signals is 5mA compared to 10mA for DC coupling.
Internal Sync Clamp
Embedded video DACs typically use ground as their most negative supply. This places the sync tip voltage at a minimum of 0V. Presenting a 0V input to most single supply amplifiers will saturate the output stage of the amplifier resulting in a clipped sync tip and degraded video image. The ISL59115 features an internal sync clamp and offset function that level shifts the entire video signal to the optimum level before it reaches the amplifiers' input stage. These features also help avoid saturation of the output stage of the amplifier by setting the signal closer to the best voltage range. The simplified block diagram on the front page shows the basic operation of the ISL59115's sync clamp. The Y and CVBS inputs' AC-coupled video sync signal is pulled negative by a current source at the input. When the sync tip goes below the comparator threshold, the comparator output goes high, pulling up on the input through the diode, forcing current into the coupling capacitor until the voltage at the input is again 0V, and the comparator turns off. This forces the sync tip clamp to always be 0V, setting the offset for the entire video signal. The C channel is slaved to the Y channel and clamped to a 500mV level.
Output Drive Capability
The ISL59115 does not have internal short circuit protection circuitry. If the output is shorted indefinitely, the power dissipation could easily overheat the die or the current could eventually compromise metal integrity. Maximum reliability is maintained if the output current never exceeds 40mA. This limit is set by the design of the internal metal interconnect. Note that for transient short circuits, the part is robust. Short circuit protection can be provided externally with a back match resistor in series with the output placed close as possible to the output pin. In video applications this would be a 75 resistor and will provide adequate short circuit protection to the device. Care should still be taken not to stress the device with a short at the output.
FN6185.2 September 21, 2006
8
ISL59115
Power Dissipation
With the high output drive capability of the ISL59115, it is possible to exceed the +125C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA
Power Supply Bypassing Printed Circuit Board Layout
As with any modern operational amplifier, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from VS+ to GND will suffice.
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance.
Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: for sourcing:
V OUT PD MAX = V S x I SMAX + ( V S - V OUT ) x --------------R
L
for sinking:
PD MAX = V S x I SMAX + ( V OUT - V S ) x I LOAD
Where: VS = Supply voltage ISMAX = Maximum quiescent supply current VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN6185.2 September 21, 2006
ISL59115 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D A B
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.45 NOMINAL 0.50 0.127 REF 0.15 2.05 1.55 0.20 2.10 1.60 0.50 BSC 0.20 0.35 0.40 10 4 1 0 12 0.45 0.25 2.15 1.65 MAX 0.55 0.05 NOTES 5 2 3 3 4 Rev. 3 6/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. Same as JEDEC MO-255UABD except: No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm "L" MAX dimension = 0.45 not 0.42mm. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
2.50 1.75
6 INDEX AREA 2X 2X 0.10 C
N
E
1 0.10 C
2
A A1
TOP VIEW
A3 b
0.10 C 0.05 C SEATING PLANE A1 SIDE VIEW (DATUM A) PIN #1 ID 1 2 NX L N (DATUM B) N-1 e 3 (ND-1) X e BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e (A1) NX b 5 A
C
D E e k L N
4xk
Nd Ne
0.10 M C A B 0.05 M C
L
TERMINAL TIP
FOR ODD TERMINAL/SIDE
b
0.05 MIN
L 2.00 0.80
0.275
0.10 MIN DETAIL "A" PIN 1 ID 0.50
0.25
LAND PATTERN 10
10
FN6185.2 September 21, 2006

▲Up To Search▲

Price & Availability of ISL59115

	To Download ISL59115 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .